1. Field of the Invention
The present invention relates to a self-alignment method applied in the field of semiconductors, in particular, to a self-alignment method for a recess channel dynamic random access memory capable of overcoming a mis-aligned problem after an exposure alignment takes place.
2. Description of Related Art
At present, optical lithography of semiconductor fabrication technology still has a size limitation to a certain extent, and the wire width cannot be reduced further due to the physical limitations of optics, so that it is difficult to enhance the resolution of pattern-transfer method. Furthermore, the smaller the size of an electronic device is, the more difficult the control of an overlay precision of a yellow light lithography is. Meanwhile, other lithographic technologies such as E-beam lithography and extreme ultraviolet (EUV) lithography also encounter bottlenecks of actual throughput, material research and development of related apparatuses.
With reference to FIGS. 1A to 1C for schematic views of a self-alignment method for a dynamic random access memory, the self-alignment method comprises the steps of:
forming a target layer 2a including a plurality of shallow trench isolation structures 11a and a plurality of recess trench channels 12a on a surface of a substrate 1a, wherein the shallow trench isolation structure 11a is disposed between the recess trench channels 12a; 
depositing a plurality of dielectric layers 3a on the target layer 2a, such that the dielectric layer 3a is formed and covered onto surfaces of the target layer 2a and the shallow trench isolation structure 11a, and the dielectric layer 3a covers and is filled into the recess trench channel 12a; 
After the dielectric layer 3a is formed, selectively performing an ion-implant process to a portion of the target layer 2a according to an electronic circuit design to form an ion-implant region 13a; and
using an exposure alignment method to selectively remove a portion of the dielectric layer 3a, and more specifically, the exposure alignment method patternizes the dielectric layer 3a by an optical lithography process and an etching process to form a plurality of structural monomers 14a protruded from the recess trench channel 12a in the target layer 2a. 
However, the foregoing method has the following drawbacks: When the exposure alignment method is carried out, it is difficult to control the overlay precision in the present process, so that a mis-aligned problem occurs after the etching process takes place, and a cell-to-cell field leakage is resulted.
In view of the aforementioned shortcomings of the prior art, the inventor of the present invention provided a reasonable design to overcome the shortcomings of the prior art.